A PLL circuit is a circuit that compares the phase of an output signal of a voltage-controlled oscillator (hereinafter referred to as VCO) with the phase of a reference signal, and feeds the comparison result back to the VCO, to stabilize the oscillation frequency of the VCO. In this PLL circuit, it is possible to output modulated waves from the VCO by performing time control on the ratio between the VCO frequency and the reference signal frequency. Accordingly, it is possible for the PLL circuit to generate the chirp signal to be used as transmission waves of a frequency modulated continuous wave (FMCW) radar, for example (see Non-Patent Literature 1, for example).
In a conventional PLL circuit that generates a chirp signal, the frequency dividing ratio at which the output of a VCO is subjected to frequency dividing by a variable frequency divider is controlled by a control circuit formed with a timing controlling circuit, a frequency accumulator, and a ΔΣ modulator, so that the chirp signal can be output from the VCO (see Non-Patent Literature 2, for example). However, in a case where a chirp signal is generated by a PLL circuit, changes in the output frequency over time are limited by a loop filter. Therefore, followability deteriorates at points where the frequency changes rapidly, for example, at portions with steep frequency gradients in sawtooth waves. To solve this problem, in a conventional PLL circuit, the output of a digital-analog converter (DAC) is added between a VCO and a loop filter, and the frequency control voltage of the VCO is made to shift at a higher speed than in the PLL loop band.